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Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
Date
Version
■
Changes
Removed the following demo boards and updated any references to them:
Cyclone II DE2 Starter board
■
Cyclone II EP2C35 board
■
Cyclone II EP2C70 board
■
November 2013
3.1
■
■
■
■
■
Stratix EP1S25 board
Stratix EP1S80 board
Stratix II EP2S60 board
Stratix II EP2S180 board
Stratix II EP2SGX90 PCI Express board
■
Updated all SOPC Builder references to Qsys.
May 2013
3.0
■
■
Added new parameter to DSP and Pipelined Adder blocks.
Added new Variable Precision DSP block
November 2012
2.1
Updated Memory Delay block parameters and signals for asynchronous entry.
June 2012
2.0
■
■
Added note on asynchronous clears
Added information on Simulink Bus Creator, Bus Selector, and Bus Assignment blocks
November 2011
1.2
Added information on Simulink simulation resets.
April 2011
1.1
■
■
Removed HIL block frame mode references
Added Virtual Pins block
June 2010
1.0
First published.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Technical support
Technical training
Product literature
Nontechnical support (general)
Contact Method
Website
Website
Email
Website
Email
Address
www.altera.com/support
www.altera.com/training
custrain@altera.com
www.altera.com/literature
nacomp@altera.com
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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